1. Field of the Invention
The present invention relates to an epitaxial tub bias structure for integrated circuits comprising at least one epitaxial tub housing regions whose potential, under certain operating conditions of the circuit, may exceed the supply voltage.
2. Discussion of the Related Art
In integrated circuits that drive inductive loads, the possibility exists that the output potential may exceed the supply voltage, which phenomenon creates serious problems in the event that the output is connected to components on the integrated circuit, such as internal resistors or PN junction capacitors. By way of illustration, FIG. 1 shows a cross section of a chip 1 of semiconductor material, comprising a P type substrate 2, and an N-type epitaxial tub 3 electrically isolated from the adjacent tubs by diffused P.sup.+ type isolation regions 4. The N-type epitaxial tub 3 also houses an elongated P-type layer 5 (forming a resistor 6 indicated by the dotted line and forming part of integrated circuit 15) terminating at either end in two P.sup.+ type regions 7, 8 on which are formed contacts 9, 10. Tub 3 also houses an N.sup.+ type region 11 on which is formed a contact 12 for biasing the tub.
In the FIG. 1 structure, if the potential of either one of the end regions of resistor 6, e.g. region 7, exceeds that of tub 3, as determined for example by contact 12, the equivalent diode formed by the PN junction between region 7 and tub 3 (shown schematically by 13) may be turned on and conduct such a high current so as to charge the parasitic equivalent capacitor formed between tub 3 and substrate 2 (shown schematically by 14), and/or turn on parasitic transistors formed by region 7, tub 3 and substrate 2, or by any other components including P type, regions integrated in tub 3, thus resulting in impaired operation of the circuit, high power loss, and even irreparable damage to this part of the integrated circuit.
Consequently, if the integrated circuit on chip 1 is designed to operate under conditions wherein the potential of either one of the P-type regions integrated in and forming a junction with tub 3 exceeds the supply voltage, the tub cannot be connected directly to the supply.
Various solutions have been devised for solving the above problem, such as providing for a floating tub or connecting it to the supply via a diode. The latter solution is shown in FIG. 2, which shows a view in perspective of a portion of a chip 18 of conducting material, again comprising a substrate 2 and an epitaxial tub 3. Tub 3 (or another tub not shown but connected electrically to tub 3) houses a P-type region 19 connected by a contact 20 to supply voltage V.sub.CC and forming a diode 21 with tub 3. Tub 3 also houses P-type region 5 forming resistor 6, one terminal of which may present a higher potential than V.sub.CC ; and a further P-type region 22 defining a further resistor 23 integrated in tub 3. In the FIG. 2 structure, regions 6, 23 and tub 3 form a parasitic PNP transistor 24, and region 5, tub 3 and substrate 2 form a further parasitic PNP transistor 25. FIG. 2 also shows two parasitic capacitors 26, 27, formed by substrate 2 and tub 3, located between the bases of parasitic transistors 24, 25 and substrate 2.
In the FIG. 2 structure, and also in the case of a floating tub, any leading edges of the potential at either one of the terminals (not shown) of resistor 6 switch on parasitic diode 13 between the terminal and tub 3 (as shown in FIG. 1). The resulting current pulse generated by the diode charges the parasitic capacitance between tub 3 and substrate 2; and, during the current pulse, the resistance of resistor 6 falls sharply so that parasitic transistor 24 and/or 25 may also be switched on. As such, the FIG. 2 structure also fails to provide a solution to the problem.
Another solution consists in forming a Schottky diode between the epitaxial tub and the P-type region whose potential may exceed the supply voltage. Schottky diodes are in fact switched on by lower direct bias voltages as compared with PN junctions, so that, when connected as described above, a Schottky diode would be switched on immediately, thus shortcircuiting the junction formed by the P region and the tub, and so preventing the parasitic diode and transistors from being switched on. Such a solution, however, is only applicable to processes that allow the formation of Schottky diodes.
It is an object of the present invention to provide a tub bias structure for preventing turn-on of the parasitic diode between the tub and the region whose potential may exceed that of the tub, and which is producible regardless of the integration process involved.